// counter_ud.v: simple up/down counter for test purposes
// 2006-06-21 E. Brombaugh

module counter_updown(
  input wire clock,
  input wire reset,
  input wire enable, 
  input wire direction, 
  output reg [7:0]  out
  //output reg [dsz-1:0] out
  );
  //parameter dsz = 8;      // counter width

  
  // synchronous binary up counter with enable
  always @(posedge clock or posedge reset)
    if(reset)
      out <= {8{1'b0}};
    else
      if(enable)
        if(direction)
          out <= out + 1'b1;
        else
          out <= out - 1'b1;
      else out <= out;
endmodule

